The invention relates generally to output ESD protection for a CMOS output buffer.
ESD (Electrostatic Discharge) protection and its impact on the reliability of IC products in submicron CMOS technologies has become a primary concern. On-chip ESD protection circuits are often connected to both the input and output pads of an IC product to avoid ESD damage. In particular, the drains of NMOS and PMOS devices in the CMOS output buffer are often directly connected to the output pad driving the external load, making the CMOS output buffer more vulnerable to ESD stress. To improve the ESD robustness of a CMOS output buffer and to handle high driving or sinking currents to and from an external heavy load, the output NMOS and PMOS devices are often designed to have large device dimensions. Even in a device having such large dimensions, the ESD robustness of a CMOS output buffer can be still seriously degraded in advanced submicron CMOS technologies. The issues of ESD robustness has been reported in the following papers:
C. Duvvury, R. N. Rountree, Y. Fong, and R. A. McPhee, "ESD phenomena and protection issues in CMOS output buffers," Proc. of IRPS, 1987, pp. 174-180. PA1 C. Duvvury and A. Amerasekera, "ESD: A pervasive reliability concern for IC technologies," Proc. of IEEE, vol. 81, no. 5, pp. 690-702, 1993. PA1 A. Amerasekera and C. Duvvury, "The impact of technology scaling on ESD robustness and protection circuit design," 1994 EOS/ESD Symp. Proc., EOS-16, pp. 237-245. PA1 C. Duvvury, R. McPhee, D. Baglee, and R. Rountree, "ESD protection in 1 .mu.m CMOS technologies," Proc. of IRPS, 1986, pp. 199-205. PA1 R. N. Rountree, "ESD protection for submicron CMOS circuits: issues and solutions," 1988 IEDM Technical Digest, pp. 508-583. PA1 C. Duvvury and R. N. Rountree, "A synthesis of ESD input protection scheme," 1991 EOS/ESD Symp. Proc., EOS-13, pp. 88-97. PA1 C. Y. Wu, M. D. Ker, C. Y. Lee, and J. Ko., "A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI," IEEE Journal of Solid-State Circuits, vol. 27, no. 3, pp. 274-280, 1992. PA1 M. D. Ker and C. Y. Wu, "Complementary-SCR ESD protection circuit with interdigitated finger-type layout for input pad of submicron CMOS IC's," IEEE Trans. Electron Devices, vol, 42, no. 7, pp. 1297-1304, 1995. PA1 A. Chatterjee and T. Polgreen, "A low-voltage triggering SCR for on-chip ESD protection at output and input pads," 1990 Proc. Symposium on VLSI Technology, pp. 75-76. PA1 A. Chatterjee and T. Polgreen, "A low-voltage triggering SCR for on-chip ESD protection at output and input pads," IEEE Electron Device Letters, vol. 12, no. 1, pp. 21-22, January 1991. PA1 M. D. Ker, K. F. Wang, M. C. Joe, Y. H. Chu, and T. S. Wu, "Area-efficient CMOS output buffer with enhanced high ESD reliability for deep submicron CMOS ASIC," Proc. of 8th IEEE International ASIC Conference and Exhibit, 1995, pp. 123-126. PA1 M. D. Ker, C. Y. Wu, M. and H. H. Chang, "Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI," IEEE Trans. Electron Devices, vol. 43, no. 4, pp. 588-598, 1996. PA1 U.S. Pat. No. 434,752, Y.-Y. B. Liu and S. Cagnina, "Electrostatic discharge protection device for CMOS integrated circuit outputs". PA1 U.S. Pat. No. 5,019,888, D. B. Scott, P. W. Bosshart, and J. D. Gallia, "Circuit to improve electrostatic discharge protection". PA1 U.S. Pat. No. 5,218,222, G. N. Roberts, "Output ESD protection circuit". PA1 U.S. Pat. No. 5,270,565, K. F. Lee, A. Lee, M. L. Marmet, and K. W. Ouyang, "electro-static discharge protection circuit with bimodal resistance characteristics". PA1 U.S. Pat. No. 5,329,143, T. C. Chan and D. S. Culver, "ESD protection circuit". PA1 C. C. Johnson, T. J. Maloney, and S. Qawami, "Two unusual HBM ESD failure mechanisms on a mature CMOS process," 1993 EOS/ESD symposium, proceedings, EOS-15, pp. 225-231.
From another practical consideration, the pin counts of high-integration CMOS VLSI/ULSI devices are often greater than 200. With such high pin-count CMOS IC's, the available layout area for each output (or input) pad with output buffer (or input ESD protection circuit) including latchup guard rings is seriously limited.
Recently, lateral SCR devices have been used as ESD-protection elements to provide input protection in submicron CMOS IC's, as described in the following papers:
The lateral SCR device was found to provide the highest ESD protection capability in a small layout area, relative to other ESD protection elements such as diodes, thick-oxide devices, gate-oxide devices, or parasitic bipolar devices in submicron CMOS IC's (see M. D. Ker, C. Y. Wu, T. Cheng, M. Wu, T. L. Yu, and A. Wang "Whole-chip ESD protection for CMOS VLSI/ULSI with multiple power pins," Proc. of 1994 IEEE International integrated Reliability Workshop, pp. 124-128). To effectively protect the CMOS output buffer, the use of a low-voltage triggering SCR (LVTSCR) device with much lower trigger voltages has been reported in the following papers:
The trigger voltage of the LVTSCR device is equivalent to the snapback-trigger voltage of a short-channel NMOS (or PMOS) device, which is inserted into the lateral SCR structure, rather than the original switching voltage (about 30.about.50V) of a lateral SCR device. The shorter channel length of the inserted NMOS (or PMOS) leads to a lower snapback-trigger voltage of the LVTSCR device.
To protect the output transistors in a CMOS output buffer, the inserted NMOS (or PMOS) in the LVTSCR device should be designed with a shorter channel length than the output NMOS (or PMOS) in the CMOS output buffer. Thus, the trigger voltage of the LVTSCR can be lower than the snapback-trigger voltage of the output NMOS (or PMOS).
Referring to FIGS. 1A, 1B and 1C, the schematic device structure, device I-V characteristics, and circuit diagram are shown, respectively, for a lateral SCR (LSCR) device which provides input ESD protection. The trigger voltage (current) of the LSCR device in the CMOS technology is about .about.50V (.about.10 mA).
Referring to FIGS. 2A, 2B and 2C, the schematic device structure, device I-V characteristics, and circuit diagram, are shown, respectively, for a modified lateral SCR (MLSCR) device which provides input ESD protection. The trigger voltage (current) of the MLSCR in the CMOS technology is about .about.25V (.about.10 mA).
Referring to FIGS. 3A, 3B and 3C, the schematic device structure, device I-V characteristics, and circuit diagram are shown, respectively, for the low-voltage-trigger lateral SCR (LVTSCR) device which provides input ESD protection. The trigger voltage (current) of the LVTSCR device in an CMOS technology is about .about.10V (.about.10 mA).
The low trigger voltage of the LVTSCR provides effective ESD protection for the CMOS output buffer. However, the lower trigger current may cause the LVTSCR to be accidentally triggered on by external overshooting or undershooting noise pulses on the input or output pins when the CMOS IC is in normal operation.
Referring to FIGS. 4A and 4B, the paths taken by an overshooting noise pulse from the input and output pads, respectively, are shown. Although the overshooting or undershooting voltage on the output pad can be clamped by forward-biased parasitic diodes which exist in the p-n junctions from the drain to the bulk of the output PMOS and NMOS devices, the trigger current of the LVTSCR device is still low for applications in noisy environments. The LVTSCR may be accidentally triggered on by an external electrical noisy pulse, due to the very low turn-on resistance of the LVTSCR, causing the input or output pads to be held at "0" and leading to the malfunction operation in the CMOS IC. Thus, in using the LVTSCR device to provide effective ESD protection for input and output pads of a CMOS IC, the LVTSCR must have a sufficient noise margin relative to the overshooting or undershooting noise pulses for safe normal operation of the CMOS IC's.